The present invention relates generally to design layout for metal layers of an integrated circuit, and more specifically to modifying the spacing between metal features that are diagonally-adjacent to one another, in order to better planarize the topology of a subsequently deposited dielectric layer over the metal features.
Conventionally designed metal line layouts of integrated circuits (IC) structures can result in large spaces between nearest parallel, electrically isolated metal lines. These spacings arc random in size and have a great variety of dimensions. When an intermetal dielectric layer (IDL), such as an oxide, is deposited over the metal lines having random spacing between them, the top surface of the IDL will have a highest altitude equal to the thickness of the metal features (Tmet) plus the thickness of the IDL (TIDL) In those areas where there are no metal features but only open space, the altitude of the top surface of the IDL will be TIDL.
FIG. 1 illustrates a side, cross-sectional view of a conventional integrated circuit structure, which includes a series of metal features 102 and an IDL 104 situated on a substrate 106. For example purposes, each metal line has a thickness, Tmet 110, and a width, Wmet 112. The thickness of IDL, TIDL, is indicated at 114. The highest altitude of the top surface of IDL 104 is Tmet+TIDL, as indicated at 116.
FIG. 1 shows IDL 104 as being non-planarized and having both wide 132 and narrow trenches 130 in the top surface of IDL 104. Where the spacing between two metal features is small, a narrow trench 130 results. Where the spacing between metal features is larger, a wider trench 132 results. FIG. 1 also shows that the surface of IDL 104 is constant in large areas where no metal features exist, such as the right-hand side of FIG. 1, showing the top surface of IDL 104 to have an altitude of TIDL, as indicated at 134. Accordingly, the prior art methods result in a nonplanar structure with heights of the IDL that vary between TIDL and Tmet+TIDL.
In order to flatten the top surface of the IDL so that subsequent metal layers can be deposited using photolithography equipment with a typical depth of focus, prior art processes then planarize the top surface of the IDL. For example, chemical mechanical polishing (CMP) techniques are commonly used to planarize the surface of an IDL.
Conventional processes often require a relatively thick IDL to guarantee an uninterrupted IDL film over the metal pattern after planarization is completed. For example, a typical IDL could have a thickness of about 12,000 angstroms when initially deposited. A planarization process would then be performed, which could remove about 7000 angstroms or more, resulting in an IDL with TIDL equal to about 5000 angstroms above the metal on average.
The conventional planarization process described above requires a relatively thick IDL layer to guarantee an uninterrupted IDL film over a metal pattern for electrical isolation. The process of depositing thick IDL layers is time consuming, and affects manufacturing yields. In addition, the planarization process itself is complicated and time consuming. The more IDL that must be removed during the planarization procedure, the longer it takes to process each wafer, resulting in lower manufacturing yields and higher costs. Accordingly, the prior art IDL planarization processes are expensive and are not as efficient as desired. In addition, the more IDL that is removed, the less consistent the thickness across the production line. This inconsistency reduces product quality as well as requiring other processing steps to cover the wider range of incoming oxide thickness (i.e., via etches, subsequent metal fills).
One might consider reducing the amount of IDL that is removed through planarization so that TIDL is greater over the metal features. However, when vias are formed through the IDL to interconnect with the metal features, these vias would have higher aspect ratios (i.e., the ratio of the vias height to its width) than if the IDL overlying the metal features were thinner. Via openings with high aspect ratios are more difficult to fill with conductive material, and thus are more likely to be defectively manufactured or prone to failure.
One method for improving on the IDL planarization process is disclosed by Wemer Juengling in U.S. Pat. No. 5,981,384, issued Nov. 9, 1999. The method involves modifying the design of a metal layer""s features to standardize the linear and diagonal spacing between nearest parallel and diagonal metal features. The design modifications yield a metal layer in which large open spaces are eliminated, and a relatively small, limited range of spaces, Smet, between nearest parallel metal features is achieved. The thickness of the IDL layer, TIDL, is optimally chosen so that the trench between parallel metal features will be substantially filled with IDL material when it is deposited, thus eliminating the need for a subsequent planarization procedure. Essentially, using the method described by Juengling, the top surface of the IDL can be xe2x80x9cself-planarized,xe2x80x9d meaning that the top surface is substantially flatter when IDL is deposited, even without a separate planarization step.
FIG. 2 illustrates a side, cross-sectional view of the metal line layout of FIG. 1 with enhanced metal features so as to standardize the spacing between the metal lines. As seen in FIG. 2, a substrate 206 has IDL 204 deposited over metal lines 202. Each metal line 202 changed width as compared to FIG. 1, by including additional features 210. These additional features 210 increase the resultant width of a metal line so that a standardized distance, Smet 220, between nearest parallel metal lines and features is achieved. In addition, electrically isolated dummy features 222 are included where large areas of spacing existed on substrate 206, within which there were no metal lines 202. By standardizing the range of spaces Smet 220, IDL 204 can be self-planarized at an altitude 224 of Tmet+TIDL, and only very narrow, xe2x80x9cfusedxe2x80x9d trenches 230 remain. As long as TIDL is sufficiently great, these fused trenches 230 are insignificantly deep, eliminating other deeper trenches, and absent other deeper trenches 130, 132 or depressed areas 134 (FIG. 1). A subsequent planarization procedure is not necessary to achieve an acceptably planar surface of IDL 204, but a slight IDL buff can be used to achieve an even more flat surface. Such a buff can improve the smoothness of subsequent metal depositions, and result in lower resistance metal lines.
FIG. 3 illustrates a top-down view of a metal line layer of an IC having standardized spacing between nearest parallel and diagonal metal features in accordance with the Juengling method. Metal lines 302 exist on a substrate within an area bounded by a guard ring 304. Additional metal line features 310 have been added to existing metal lines 302 in order to standardize the spacing between nearest parallel and diagonal metal features. In addition, electrically isolated dummy features 322 have been added within the open space in which there are no metal lines.
Juengling states that the standard distance, Smet 320, between nearest parallel metal features must be xe2x89xa62*TIDL. The reason for this is that most of the space between parallel metal features will be substantially filled with IDL material if Smet is less than 2*TIDL, assuming perfect step coverage. Accordingly, even without a separate planarization process, only fused trenches (e.g., trench 230, FIG. 2) should exist on the top surface of the IDL between the parallel metal features. The optimum space, Smet, gets reduced for less than perfect step coverage IDL depositions. In addition, it is desirable to keep TIDL as low as possible so that vias that are subsequently formed through the IDL will not have an unreliably high aspect ratio.
Limitations of the Juengling method are apparent, however, in areas such as areas 350 and 370, where an xe2x80x9cintersectionxe2x80x9d of spaces between metal features exists. FIG. 4 illustrates an enlarged, top-down view of area 350 of the metal line layout of FIG. 3, illustrating the effect on an IDL in an area where a four-way intersection of metal features 402, 404, 406, 408 exists.
As described previously, according to the Juengling method, the distance between parallel metal features (e.g., features 404, 406) is Smet 410, which is optimally xe2x89xa62*TIDL. The distance between nearest diagonal features (e.g., features 402, 406) is Smetdrag 420, which is approximately {square root over (2)}*Smet. When the constraint is used that Smetxe2x89xa62*TIDL, then Smetdrag must be xe2x89xa62{square root over (2)}*TIDL. Dashed IDL contour lines 430 illustrate where the top surface of the IDL will start to droop when Smet approximately equals 2*TIDL, where TIDL is indicated by reference number 440. Between parallel features (e.g., features 402, 404 or 406, 408), no significant droop will occur, and a fused trench akin to trench 230 (FIG. 2) will exist. However, between diagonal features (e.g., features 402, 406), a substantial droop will occur, and a depression, akin to trenches 130 or 132 (FIG. 1), will exist on the top surface of the IDL, as indicated by region 450. The altitude of the surface of the IDL within the depression 450 can approach TIDL.
A similar phenomenon occurs in regions where two-way and three-way intersections exist. FIG. 5 illustrates an enlarged, top-down view of area 370 of the metal line layout of FIG. 3, illustrating the effect on an IDL in an area where a three-way intersection exists. Dashed IDL contour lines 530 illustrate where the top surface of the IDL will start to droop when Smet 510 equals 2*TIDL, where TIDL is indicated by reference number 540 (again, for perfect step coverage). Between parallel features (e.g., features 502, 504 or 502, 506), no significant droop will occur, and a fused trench akin to trench 230 (FIG. 2) will exist. However, in the center of the intersection, a substantial droop will occur, and a depression, akin to trenches 130 or 132 (FIG. 1), will exist on the top surface of the IDL, as indicated by region 550.
These trenches 450, 550 (FIGS. 4, 5) present in regions with intersections or metal feature corners reduce the flatness of the top surface of the IDL. This necessitates using a thicker IDL layer in order to reduce or eliminate the depressions. A thicker IDL means that the aspect ratio of subsequently formed vias will be higher, unless a separate planarization procedure is used to reduce the IDL thickness. Both a thicker IDL and a separate planarization procedure add cost and complexity to the manufacturing process, as well as reducing yields.
Manipulation of the governing equations further clarifies the issues. In order to achieve self-planarization between parallel metal features, then TIDLxe2x89xa70.5*Smet (because Smetxe2x89xa62*TIDL). However, in order to achieve self-planarization between diagonal metal features, then TIDLxe2x89xa70.5*Smetdrag. According to this constraint, and since Smetdrag≈{square root over (2)}*Smet, then in order to achieve complete self-planarization, TIDLxe2x89xa70.5*({square root over (2)}*Smet), or TIDLxe2x89xa7({square root over (2)}/2)*Smet.
In other words, the Juengling method will result in a self-planarized IDL for 0.5*Smetxe2x89xa6TIDLxe2x89xa6({square root over (2)}/2)*Smet when only parallel metal features exist. However, TIDL must be xe2x89xa7({square root over (2)}/2)*Smet to achieve a fully self-planarized IDL, when the metal layer includes intersections. Therefore, when the metal layer includes such intersections, the IDL must be made thicker and the aspect ratio of subsequently formed vias will be higher, absent a separate planarization procedure.
Accordingly, what are needed are metal feature designs and manufacturing methods where the top surface of an IDL is self-planarized, even in regions where intersections exist. Further needed arc metal feature designs and manufacturing methods that achieve this self-planarization using an IDL that is as thin as possible, so that the aspect ratio of subsequently formed vias is as low as possible.
Embodiments of the present invention provide a metal feature structure that eliminates the need for a separate planarization procedure or a thicker IDL. In addition, embodiments provide a method for fabricating the structure on an integrated circuit, such as a dynamic random access memory (DRAM).
For one embodiment, the invention provides a method for fabricating an integrated circuit structure. The method includes depositing a conductive layer above an insulating material, and patterning the conductive layer to form a plurality of first metal features and at least one second metal feature. The first metal features and the at least one second metal feature have a substantially equal thickness, Tmet, above the insulating material, and the first metal features have a substantially standard distance, Smet, between parallel edges of adjacent ones of the first metal features. The at least one second metal feature is connected to one or more of the first metal features in proximity to an intersection area of the conductive layer. An intersection area is a roughly rectangular area that includes at least one metal feature corner, parts of at least one other metal feature that are in close proximity to the at least one metal feature corner, and a portion of a dielectric layer that will be located between the at least one metal feature corner and the parts of the at least one other metal feature. The method also includes depositing the dielectric layer having a thickness, TIDL, over the conductive layer.
For another embodiment, the method includes forming a portion of a semiconductor device, which includes a layer of insulating material that defines a top surface of the portion of the semiconductor device, depositing a conductive layer above the layer of insulating material, and patterning the conductive layer to form a plurality of first metal features and at least one second metal feature. The first metal features and the at least one second metal feature have a substantially equal thickness, Tmet, above the insulating material, and the first metal features have a substantially standard distance, Smet, between parallel edges of adjacent ones of the first metal features. The at least one second metal feature is connected to one or more of the first metal features in proximity to an intersection area of the conductive layer. An intersection area is a roughly rectangular area that includes at least one metal feature corner, parts of at least one other metal feature that are in close proximity to the at least one metal feature corner, and a portion of a dielectric layer that will be located between the at least one metal feature corner and the parts of the at least one other metal feature. The method further includes depositing the dielectric layer having a thickness, TIDL, over the conductive layer.
For yet another embodiment, the method includes depositing a conductive layer above an insulating material, and patterning the conductive layer to form a plurality of first metal features and at least one second metal feature. The first metal features and the at least one second metal feature have a substantially equal thickness, Tmet, above the insulating material, and the first metal features have a substantially standard distance, Smet, between parallel edges of adjacent ones of the first metal features. The at least one second metal feature is connected to one or more of the first metal features in proximity to an intersection area of the conductive layer. An intersection area is a roughly rectangular area that includes at least one metal feature corner, parts of at least one other metal feature that are in close proximity to the at least one metal feature corner, and a portion of a dielectric layer that will be located between the at least one metal feature corner and the parts of the at least one other metal feature. The intersection area includes the parts of the at least one other metal feature that are within a distance of roughly {square root over (2)}*Smet from the at least one metal feature corner. The method further includes depositing the dielectric layer having a thickness, TIDL, over the conductive layer.
For a further embodiment, the method includes depositing a conductive layer above an insulating material, and patterning the conductive layer to form a plurality of first metal features and at least one second metal feature. The first metal features and the at least one second metal feature have a substantially equal thickness, Tmet, above the insulating material, and the first metal features have a substantially standard distance, Smet, between parallel edges of adjacent ones of the first metal features. The at least one second metal feature is connected to one or more of the first metal features in proximity to an intersection area of the conductive layer. An intersection area is a roughly rectangular area that includes at least one metal feature corner, parts of at least one other metal feature that are in close proximity to the at least one metal feature corner, and a portion of a dielectric layer that will be located between the at least one metal feature corner and the parts of the at least one other metal feature. The method further includes depositing the dielectric layer over the conductive layer, where the dielectric layer has a thickness, TIDL, where 0.5*Smetxe2x89xa6TIDLxe2x89xa6({square root over (2)}/2)*Smet.
Further embodiments of the invention include semiconductor structures produced using one or more methods of the invention, as well as apparatus, devices, modules and systems making use of such semiconductor structures.